The present invention generally relates to a method for fabricating a semiconductor device, and more particularly relates to a hydrogen sintering process for making a processed object recover from process-induced damage.
A so-called "hydrogen sintering process", i.e., a heat treatment within hydrogen ambient, has been conducted to repair the damage caused in a gate oxide film, for example, by dry etching, metal film sputtering and so on during the fabrication process of a semiconductor device. Hereinafter, the conventional hydrogen sintering process will be described.
FIG. 7 is a cross-sectional view illustrating an exemplary semiconductor device, which is an object of a hydrogen sintering process. In FIG. 7, a part of a substrate, on which a second interlevel dielectric film 16 has been formed during a fabrication process of the semiconductor device with a tungsten plug structure, is illustrated. As shown in FIG. 7, an interlevel dielectric film 12 is formed between a diffused layer 11 within a silicon substrate 10 and an aluminum alloy interconnection layer 15. A contact hole is provided within the interlevel dielectric film 12 to electrically connect the aluminum alloy interconnection layer 15 to the diffused layer 11. A barrier metal layer 13, which is a stack of titanium and titanium nitride films or tantalum and tantalum nitride films, is formed on the inner faces of the contact hole and on the surrounding region of the interlevel dielectric film 12. The contact hole is filled in with a metal film of tungsten, for example, on the barrier metal layer 13, thereby forming a buried layer 14 with a plug structure. The second interlevel dielectric film 16 is further provided on the aluminum alloy interconnection layer 15 to form a second aluminum interconnection layer (not shown) over the layer 15.
Recently, such a tungsten plug structure, in which a contact hole provided within an interlevel dielectric film is filled in with tungsten as a contact member for connecting a pair of interconnection lines together or an interconnection line to an underlying substrate, is a very common structure.
In the conventional semiconductor device fabrication process, after the structure shown in FIG. 7 has been formed, a so-called hydrogen sintering process, i.e., a heat treatment within hydrogen ambient, is conducted. The sintering process is conducted to reduce a contact resistance between the barrier metal layer 13 and the diffused layer 11 or to repair the damage caused in a gate oxide film, for example, by dry etching or metal film sputtering for an MOS semiconductor device, in particular. In the conventional semiconductor device fabrication process, the hydrogen sintering process is conducted as a batch heat treatment by introducing several tens of semiconductor substrates (or wafers) at a time into a batch diffusion furnace made of a quartz tube, for example, and provided with a hydrogen gas supply line. Such a method of conducting hydrogen sintering on a great number of wafers at a time will be called a "batch hydrogen sintering process" for convenience. According to the conventional technique, the interface of the gate oxide film in an MOS transistor is allegedly stabilized by conducting the batch hydrogen sintering process.
If such a great number of wafers are sintered at a time within a thermal diffusion furnace according to the conventional hydrogen sintering technique, however, a very long time, e.g., about two and a half hours, is needed for single treatment cycle, and is far from being productively efficient. Generally speaking, the size of a single chip will be further increased from now on to catch up with the performance enhancement trend of a semiconductor integrated circuit. In addition, the size of a single wafer will also be further increased to cut out a greater number of semiconductor chips from a single wafer and thereby cut down the chip manufacturing cost.
Under the circumstances such as these, if such a wafer of a greater size is sintered with hydrogen in a batch thermal diffusion furnace as is done in the conventional method, then the distribution of temperatures within the wafer plane will get increasingly non-uniform. Accordingly, when the wafer is introduced into the furnace, various crystal lattice defects are more likely to be caused within the wafer due to the non-uniform temperature distribution within the wafer plane. Various countermeasures have been suggested to ensure sufficient response or uniformity for the temperature of the wafer being introduced into the furnace. For example, according to a proposed technique, a speed, at which a wafer-carrying boat is introduced into, or taken out of, the core of the furnace, is decreased intentionally. As an alternative, a process step of lowering the temperature at the core of the furnace is additionally provided before the wafer-carrying boat is introduced into, or taken out of, the core of the furnace. However, according to any of these techniques, the heat treatment should be conducted for an even longer time, and therefore, the productivity further declines.